B.Tech. III Semester
Examination, December 2023
Grading System (GS)
Max Marks:
70 | Time: 3 Hours
Note:
i) Attempt any five questions.
ii) All questions carry equal marks.
iii) Assume suitable data, if required.
a) Perform the following conversions: (Unit 1)
i) Add $(83)_{10}$ and $(34)_{10}$ in BCD.
ii) Convert the base-7 number $(35614)_7$ to base-12.
b) Explain how the basic gates can be realized using NOR gates? (Unit 1)
a) Design a Half adder circuit with truth table and logic diagrams. (Unit 2)
b) A combinational circuit is defined by the following Boolean functions. Design circuit with a decoder and external gates: (Unit 2)
$F_1(x, y, z) = x'y'z' + xz$
$F_2(x, y, z) = xyz' + x'z$
a) Explain the working of the master slave JK flip-flop. (Unit 3)
b) Design a 3-bit binary UP/DOWN counter with a direction control M, Use T flip-flop. (Unit 3)
a) Draw and explain the PMOS, NMOS and CMOS logic. (Unit 4)
b) Explain how a Schmitt Trigger circuit works with a neat diagram. Design an Schmitt trigger with $V_{UT} = 2V$, $V_{LT} = -1V$. Assume $+V_{sat} = + 13V$, $-V_{sat} = -13V$. (Unit 4)
a) What is mutual information and how it is related to channel capacity? For a standard voice band communication channel the signal to noise ratio is 30dB and transmission bandwidth is 3 KHz. What will be the Shannon limit for information in bits/sec? (Unit 5)
b) Explain BFSK modulation schemes. (Unit 5)
a) Reduce the expression $Y = \Sigma m (1, 4, 8, 12, 13, 15) + d (3, 14)$ using K-maps and implement the real minimal expression using basic logic gates. (Unit 1)
b) What are the different types of parallel adders? Explain carry save and carry look-ahead adders. (Unit 2)
a) Derive the frequency of oscillation of an astable multivibrator using IC 555 timer. (Unit 4)
b) Explain: DRAM and FLASH RAM. (Unit 3)
a) An 8-bit D/A converter has a resolution of 10mV/bit. Find the analog output voltage for the inputs: (Unit 4)
i) 10001010
ii) 00010000
b) Describe the operation of dual slope A/D converter with necessary diagrams. (Unit 4)