B.Tech. III Semester
Examination, December 2025
Grading System (GS)
Max Marks:
70 | Time: 3 Hours
Note:
i) Attempt any five questions.
ii) All questions carry equal marks.
a) Convert the following: (Unit 1)
i) $(753)_8$ to decimal
ii) $(4A3)_{16}$ to binary
iii) $(101101.101)_2$ to decimal
iv) $(45.625)_{10}$ to Binary
v) $(110101101)_2$ to Hexadecimal
vi) $(74)_{10}$ to Excess-3 code
vii) $(1101101)_2$ to Gray code
a) Implement the Boolean function using only NAND gates:
$F(A,B,C)=AB+A'C$ (Unit 1)
b) Simplify the following function using 3-variable K-map:
$F(A,B,C)=\sum m(1,2,3,5,7)$
Also draw the simplified logic diagram. (Unit 1)
a) Implement the Boolean function $F(A,B,C)=\sum m(1,3,6,7)$ using a 4:1 multiplexer. (Unit 2)
b) Design a decimal-to-BCD encoder and explain its working. (Unit 2)
a) Explain the working of a Master-Slave J-K flip-flop with timing diagram. (Unit 3)
b) Explain asynchronous counters and synchronous counters. Compare them with respect to speed and hardware complexity. (Unit 3)
a) Implement the Boolean functions using PLA:
$F1 = A'B + AC$
$F2 = AB + BC'$
Draw the PLA programming table. (Unit 3)
b) Explain the working of a Sample and Hold circuit with neat diagram. Why is it required in ADC systems. (Unit 4)
a) Explain the internal block diagram and working of IC 555 Timer. Discuss any two applications of IC 555. (Unit 4)
b) Explain the need for interfacing between TTL and MOS logic. Discuss TTL-to-CMOS interfacing techniques. (Unit 4)
a) Explain Time Division Multiplexing (TDM) with block diagram. Differentiate between synchronous and asynchronous TDM. (Unit 5)
b) Explain quantization process and quantization error in PCM. How can quantization noise be reduced. (Unit 5)
Write a short note on any two:
a) Logic Gates (Unit 1)
b) look-ahead carry generator (Unit 2)
c) S-R Flip-Flop (Unit 3)
d) Shannon's Channel Capacity Theorem (Unit 5)