B.Tech. IV Semester
Examination, June 2024
Grading System (GS)
Max Marks: 70 | Time: 3 Hours
Note:
i) Attempt any five questions.
ii) All questions carry equal marks.
a) Explain the role and significance of registers in a CPU's general register organization. (Unit 1)
b) Differentiate between Hardwired control unit and Micro-programmed control unit. (Unit 2)
a) What is register transfer language? Explain the representation of instructions in register transfer language with suitable examples ? (Unit 1)
b) Discuss how two's complement is used for representing negative numbers and performing subtraction as addition with complement. (Unit 3)
a) Discuss how binary division is performed and the steps involved in dividing one binary number by another with flowchart. (Unit 3)
b) Design a 4-bit adder/subtractor circuit and explain how addition and subtraction are performed ? (Unit 3)
a) Why interface is needed in input output device? Explain how it is connected to I/O devices with neat sketch? (Unit 4)
b) Describe the strobe control and hand shaking methods in asynchronous data transfer. (Unit 4)
a) What is the need of I/O processor? Explain the working of I/O processor? (Unit 4)
b) Discuss the different types of secondary memory devices commonly used in computer systems, such as Hard Disk Drives (HDDs), magnetic tapes, and optical discs. Compare the advantages and disadvantages of each type. (Unit 5)
a) Define cache memory and explain its role in improving CPU performance. Discuss the principles of locality (temporal and spatial) and how they influence cache effectiveness. (Unit 5)
b) Describe the role of the Memory Management Unit (MMU) in a computer system. Explain how the MMU facilitates address translation between virtual addresses and physical addresses. (Unit 5)
a) Define RISC and CISC architectures and explain their fundamental differences. (Unit 6)
b) Discuss how pipelining improves instruction execution throughput and overall system performance in processors. (Unit 6)
Write a short note on any two of the following:
a) Bus structure (Unit 1)
b) SCSI Bus (Unit 4)
c) Random Access Memory (Unit 5)
d) Inter processor arbitration (Unit 6)